1. Field of the Invention
The invention relates to semiconductor devices and methods for construction thereof. In particular, the invention relates to using different contact sizes at different layers of the semiconductor device in order to simplify and improve manufacturing techniques.
2. Related Art
In building semiconductor devices, such as NAND gates or other logic gates, it is necessary to make contact with various layers of the semiconductor device. This includes making contact with the first or second polysilicon layers or the silicon core. FIG. 1 is an example of one such device. As shown in FIG. 1, a silicon core 101 has overlaid thereon a first polysilicon layer 103 which stores electrons. An oxide layer 102 can also be used between the silicon core 101 and the first polysilicon layer 103. Polysilicon layer 103 is covered by a dielectric layer 105. Dielectric Layer 105 is typically made up of an oxide layer 107, a nitride layer 109 and another oxide layer 110. Dielectric layer 105 has a second polysilicon layer 111 thereon. This layer often serves as the gate or word line where voltage is applied to turn on selected cells. The second polysilicon layer 111 also has thereon a tungsten silicide layer 113. These layers are covered by an interlayer dielectric (ILD) 115, which is polished to a uniform thickness. Metal interconnection lines 117 are then formed on top of the ILD 115.
FIG. 1 also illustrates contact 119 contacting the core layer, contact 121 contacting the P1 layer, and contact 123 contacting the P2 layer. In conventional semiconductor devices, each of these contacts is the same size. Although each contact is the same size, it is necessary to etch different amounts of material to achieve the contacts at the different depths shown in FIG. 1. For example, where the pattern is manufactured into each layer and the ILD material subsequently applied, the ILD must be etched away to a different depth for contacts 119, 121 and 123. Conventional systems attempt to achieve the uniform contact size by adjusting etch process parameters, such as chamber pressure, temperature or other parameters. This approach results in a complex manufacturing process, which is subject to error in etching to the correct depth.